Design and Simulation of Junctionless Double Gate Graphene FET

N. Sai kiran , K. Jeevan Reddy

Junctionless Double gate FET, Graphene, high-k materials, leakage current, short channel effects, SS.

This paper presents the design and simulation of junctionless double gate graphene FET. This design uses the new materials which have high K. Without suffering serious short channel effects, the designed JL DG graphene device shows excellent characteristics. The designed device shows reduced leakage current, Small SS, high ION/IOFF. The results obtained show the improvement in the transistor performance for certain parameters.

Published Paper   E-Certificate

"Design and Simulation of Junctionless Double Gate Graphene FET", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.1, Issue 11, page no.57 - 61, November-2016, Available :https://ijsdr.org/papers/IJSDR1611010.pdf

Volume 1 Issue 11, November-2016

Pages : 57 - 61

Paper Reg. ID: IJSDR_160928

Published Paper Id: IJSDR1611010

Downloads: 000347459

Research Area: Engineering

Country: Hyderabad, Telangana, India

Published Paper PDF: https://ijsdr.org/papers/IJSDR1611010

Published Paper URL: https://ijsdr.org/viewpaperforall?paper=IJSDR1611010

ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Publisher: IJSDR(IJ Publication) Janvi Wave

This work is licensed under a Creative Commons Attribution 4.0 International License and The Open Definition