Low power VLSI design techniques- A detailed review.

Sakshi Gupta

Low Power, Abstraction Level.

Power dissipation has emerged as an important design parameter in the design of VLSI chips, especially in portable computing and personal communication applications. This paper discusses in detail the various low power dissipation techniques used at different levels of abstractions. It also focuses on the recent new techniques developed for lowering the power dissipation in a VLSI chip and adopted widely by the industry

Published Paper   E-Certificate

"Low power VLSI design techniques- A detailed review.", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.1, Issue 6, page no.292 - 295, June-2016, Available :https://ijsdr.org/papers/IJSDR1606052.pdf

Volume 1 Issue 6, June-2016

Pages : 292 - 295

Paper Reg. ID: IJSDR_160485

Published Paper Id: IJSDR1606052

Downloads: 000347317

Research Area: Engineering

Country: PUNE, MAHARASHTRA, India

Published Paper PDF: https://ijsdr.org/papers/IJSDR1606052

Published Paper URL: https://ijsdr.org/viewpaperforall?paper=IJSDR1606052

ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Publisher: IJSDR(IJ Publication) Janvi Wave

This work is licensed under a Creative Commons Attribution 4.0 International License and The Open Definition