Design of SRAM Memories with Different Topologies

Nirmala S O , Leela G H , Aniket Vilas Vakude , Dharani A S

SRAM, 6T, 9T, 10T, low power consumption, high-speed performance

This paper presents a comprehensive analysis of three static random access memory (SRAM) cell designs: 6T, 9T, and 10T. The purpose of the analysis is to determine the most suitable SRAM cell for attaining low power consumption and high-speed performance. Each cell design is evaluated based on various parameters, including write access time and power dissipation. The results obtained from the analysis provide valuable insights into the trade-offs between power consumption and performance, enabling the selection of an optimal SRAM cell for specific design requirements.

Published Paper   E-Certificate

"Design of SRAM Memories with Different Topologies", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.8, Issue 10, page no.168 - 171, October-2023, Available :https://ijsdr.org/papers/IJSDR2310030.pdf

Volume 8 Issue 10, October-2023

Pages : 168 - 171

Paper Reg. ID: IJSDR_208756

Published Paper Id: IJSDR2310030

Downloads: 000347207

Research Area: Engineering

Country: Davangere, Karnataka, India

Published Paper PDF: https://ijsdr.org/papers/IJSDR2310030

Published Paper URL: https://ijsdr.org/viewpaperforall?paper=IJSDR2310030

DOI: https://doi.org/10.5281/zenodo.10446592

ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Publisher: IJSDR(IJ Publication) Janvi Wave

This work is licensed under a Creative Commons Attribution 4.0 International License and The Open Definition