Vlsi design of advanced-features aes crypto processor for data cryptography
Rashmi A
, Dr. Yogesh G S
AES is a mathematical justification of data concealment. It involves implementation on the very secure symmetric cryptography method using an FPGA (field-programmable gate array). This projected construction consists of an 8-bit stream of data and five primary components. We design two separate registration banks, Key-Register and State-Register, to hold the plain text, the keys, and intermediate data. To save space, shift-rows are added to the state register. We developed an 8-bit block that can transmit and receive 8-bit data and has four inner registers that are optimised for Mix-Columns. To make different Sub-Bytes better, we integrate and simplify them. To reduce power usage, we use clock gate technology into the architecture. For picture cryptography, this work proposes a 128-bit AES architecture.Verilog HDL is castoff create this design, and a Matlab& Modelsim 6.4 C tool are used to simulate it. The Synthesis Process tool from Xilinx measures performance.
"Vlsi design of advanced-features aes crypto processor for data cryptography", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.8, Issue 8, page no.588 - 593, August-2023, Available :https://ijsdr.org/papers/IJSDR2308086.pdf
Volume 8
Issue 8,
August-2023
Pages : 588 - 593
Paper Reg. ID: IJSDR_208230
Published Paper Id: IJSDR2308086
Downloads: 000347153
Research Area: Engineering
Country: Bangalore, Karnataka, India
ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publisher: IJSDR(IJ Publication) Janvi Wave
