Design and implementation of high-speed adaptive filter for speech enhancement
SRI.B.MYSURA REDDY
, SK.RIJWANA , T.Sai Dinesh Reddy
FPGA,retimed,adaptive filter,voice enhancemnt,noise cancellation,filtering,clock speed,hardware requirements,delay,vlsi,algorithm,power consumption,operating frequency,maximum combinational path delay,latency
The FPGA implementation of retimed high speed adaptive filter architectures for voice enhancement is shown in this research. Many high-speed adaptive filtering techniques for noise cancellation are implemented in this work. The clock speed, hardware requirements, delay, and cost of various VLSI implementations have been seen to vary significantly. The VLSI implementation and performance analysis provide critical information about the structure of an algorithm, such as hardware requirements, power consumption, and real-time performance. The implemented structures' performance was evaluated in terms of operating frequency, maximum combinational path delay, latency, and power consumption.
"Design and implementation of high-speed adaptive filter for speech enhancement", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.8, Issue 3, page no.1162 - 1167, March-2023, Available :https://ijsdr.org/papers/IJSDR2303191.pdf
Volume 8
Issue 3,
March-2023
Pages : 1162 - 1167
Paper Reg. ID: IJSDR_204794
Published Paper Id: IJSDR2303191
Downloads: 000347196
Research Area: Electronics & Communication Engg.
Country: kadapa, Andhra Pradesh, India
ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publisher: IJSDR(IJ Publication) Janvi Wave
