Implementation of an efficient full adder Using Systematic Cell Design Methodology
Anila Susan George
, Jyothish Chandran G , Anu Raj
Systematic cell design methodology, three input XOR/XNOR,full adder, transmission gate, low power high performance
In this paper, an efficient full adder using Systematic Cell Design Methodology (SCDM) is explained. The design is first implemented for 1 bit and then extended to 4 bit also. The circuit was implemented using Mentor Graphics tools at 180 nm technology. Performance parameters like average power, average propagation delay and Power Delay Product (PDP) are compared with existing hybrid adders like FADPL and FASRCPL. The proposed adder has less number of transistors in the critical path leading to less propagation delay. The use of transmission gate throughout the design ensures high driving capability and full voltage swing at the output. The proposed adder is found to be working efficiently when compared to other adders in terms of average power, average propagation delay and PDP.
"Implementation of an efficient full adder Using Systematic Cell Design Methodology ", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.1, Issue 7, page no.267 - 270, July-2016, Available :https://ijsdr.org/papers/IJSDR1607046.pdf
Volume 1
Issue 7,
July-2016
Pages : 267 - 270
Paper Reg. ID: IJSDR_160637
Published Paper Id: IJSDR1607046
Downloads: 000346998
Research Area: Engineering
Country: Kottayam, Kerala, India
ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publisher: IJSDR(IJ Publication) Janvi Wave
