A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor
M. Raj Lahari
, K. Neeharika
Decoder, Delay, Garbage Output, Low Power Design, Quantum Cost, Reversible & Fault Tolerant Computing.
This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the number of data bits.The circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant inputs, garbage outputs and quantum cost of the reversible fault tolerant decoder have been proposed. Transistor simulations of the proposed decoder are shown using standard p-MOS 901 and n-MOS 902 model with delay of 0.030 ns and 0.12 μm channel length, which proved the functional correctness of the proposed circuits. The comparative results show that the proposed design is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability than the existing approach.
"A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.1, Issue 6, page no.142 - 147, June-2016, Available :https://ijsdr.org/papers/IJSDR1606029.pdf
Volume 1
Issue 6,
June-2016
Pages : 142 - 147
Paper Reg. ID: IJSDR_160509
Published Paper Id: IJSDR1606029
Downloads: 000347319
Research Area: Engineering
Country: Unknown, Unknown, India
ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publisher: IJSDR(IJ Publication) Janvi Wave
