A Low Power 4X 4 Multiplier Design using (5-T)Half Adder,(8-T)Full Adder &(2-T) AND Gate
Prof. M.Raj Lahari
, Prof. K.Neeharika
2-T AND; 8-T Full Adder; 4x4 Multiplier; 2-T MUX; Pass transistor logic; 3-T XOR;
In this paper, we propose a new technique for implementing a low power high speed multiplier using full adder consisting of minimum no. of transistors (8-T). Multiplier circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the multiplier. Simulated results indicate the superior performance of the proposed technique over conventional CMOS multiplier. Detailed comparison of simulated results for the conventional and present method of implementation is presented.
"A Low Power 4X 4 Multiplier Design using (5-T)Half Adder,(8-T)Full Adder &(2-T) AND Gate", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.1, Issue 5, page no.506 - 510, May-2016, Available :https://ijsdr.org/papers/IJSDR1605097.pdf
Volume 1
Issue 5,
May-2016
Pages : 506 - 510
Paper Reg. ID: IJSDR_160372
Published Paper Id: IJSDR1605097
Downloads: 000347059
Research Area: Engineering
Country: Unknown, Unknown, India
ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publisher: IJSDR(IJ Publication) Janvi Wave
