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Paper Title: Survey of Scan Chain based Low Power Testing
Authors Name: Rashmi K.M , Dr.K.N.Muralidhara
Unique Id: IJSDR1607020
Published In: Volume 1 Issue 7, July-2016
Abstract: In the area of VLSI testing chip failure can occur anywhere, it can be in the flip flops, combinational circuitry or even the Design for testability (DFT) circuitry such as scan chain and logic BIST. Scan chains can be touted as effective aid for logic circuit testing and diagnosis and maximum chip failures occurs due to the defects in the scan chains. This survey is mainly focused on the scan chain defects and scan chain masking for diagnosis of failures in scan based testing.
Keywords: BIST, Design for testability, scan chain masking, scan based testing
Cite Article: "Survey of Scan Chain based Low Power Testing", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.1, Issue 7, page no.125 - 127, July-2016, Available :http://www.ijsdr.org/papers/IJSDR1607020.pdf
Downloads: 0001419
Publication Details: Published Paper ID: IJSDR1607020
Registration ID:160605
Published In: Volume 1 Issue 7, July-2016
DOI (Digital Object Identifier):
Page No: 125 - 127
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631

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