INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15
Using a combination of Pass Transistor Logic (PTL), CMOS logic, and transmission gate (TG) logic in 65-nm technology, a unique Hybrid Full Adder (HFA) has been developed. This implementation includes various modules such as the XOR module, the carry generator module, and the sum generator module, which are used to realize a 1-bit HFA. To design the proposed HFA, an inverter logic is used in conjunction with the XOR logic to obtain the logic of XNOR. The proposed design is impressive as it uses only 13 transistors, resulting in a small area. This improvement in terms of Power-Delay Product (PDP) makes it suitable for basic building blocks of Very Large-Scale Integration (VLSI) circuits. Furthermore, the power consumption of the proposed HFA is significantly lower, resulting in improved PDP compared to other hybrid full adders. A comparison of the essential parameters between the proposed HFA and other existing HFAs has been made.
Keywords:
Hybride full adder ,XOR Gate, XNOR gate,
Cite Article:
"A HYBRID FULL ADDER USING A NOVAL XOR GATE FOR LOW POWER APPLICATION", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.8, Issue 4, page no.2741 - 2746, April-2023, Available :http://www.ijsdr.org/papers/IJSDR2304426.pdf
Downloads:
000337070
Publication Details:
Published Paper ID: IJSDR2304426
Registration ID:205910
Published In: Volume 8 Issue 4, April-2023
DOI (Digital Object Identifier):
Page No: 2741 - 2746
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631
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