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INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH
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ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
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Paper Title:	A Review on Implementation of AES Algorithm Using FPGA
Authors Name:	Asawari Ujjainkar , Prof. A.B. Kharate
Unique Id:	IJSDR2301186
Published In:	Volume 8 Issue 1, January-2023
Abstract:	Now a day’s large number of internet and wireless communication users has led to an increasing demand of security measures and devices for protecting the user data transmitted over the unsecured network so that unauthorized persons cannot access it . As we share the data through wireless network it should provide data confidentiality, integrity and authentication. The symmetric block cipher plays a major role in the bulk data encryption. Advanced Encryption Standard (AES) provides data security. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has lot of advantage such has increased throughput and better security level. Hardware Implementation for 128 bit AES (Advanced Encryption Standard) encryption and Decryption has been made using VHDL. The proposed algorithm for encryption and decryption module will functionally verified using modelsim, will be synthesize using Quartus 2 using Altera FPGA platform and analyze the design for the power, Throughput & area.
Keywords:	AES, Encryption, Decryption, FPGA, VHDL, Security
Cite Article:	"A Review on Implementation of AES Algorithm Using FPGA", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.8, Issue 1, page no.1180 - 1185, January-2023, Available :http://www.ijsdr.org/papers/IJSDR2301186.pdf
Downloads:	000337061
Publication Details:	Published Paper ID: IJSDR2301186 Registration ID:203757 Published In: Volume 8 Issue 1, January-2023 DOI (Digital Object Identifier): Page No: 1180 - 1185 Publisher: IJSDR \| www.ijsdr.org ISSN Number: 2455-2631

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