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INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016 open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15 |
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| Paper Title: | Design Model of Retiming Multiplier for FIR Filter and its Verification |
| Authors Name: | DONDA KATYAYANI , PRADEEP KONDAPALLI |
| Unique Id: | IJSDR2104117 |
| Published In: | Volume 6 Issue 4, April-2021 |
| Abstract: | In recent years in VLSI technologies Multiplication operation cause great rating Digital type filters. The main objective is to increase the speed and reduce the delay as well as power consumption. Low and reduced power consumption with better performance, Architecture based on the retaining multiplier for finite impulse response. The design of a low-voltage micropower asynchronous (async) signed truncated multiplier based on a shift–add structure for power-critical applications such as the low-clock-rate (4 MHz) hearing aids is described. The emphases of the design are micropower operation and small IC area, and these attributes are achieved in several ways. An error correction methodology is proposed to mitigate, where appropriate, the arising truncation errors. The errors arising from truncation and the effectiveness of the error correction are analytically derived. Third, a low-power shifter design and an internal latch adder are adopted. Finally, a power-efficient speculative delay line is proposed to time the async operation of the various circuit modules. A comparison with competing synchronous and async designs shows that the proposed design features the lowest power dissipation (5.86 W at 1.1 V and 1 MHz) and a very competitive IC area (0.08 mm using a 0.35- m CMOS process). The application of the proposed multiplier for realizing a digital filter for a hearing aid is given. |
| Keywords: | Asynchronous (async) circuits, finite-impulse response (FIR) filter, low power, shift–add multiplier |
| Cite Article: | "Design Model of Retiming Multiplier for FIR Filter and its Verification", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.6, Issue 4, page no.700 - 704, April-2021, Available :http://www.ijsdr.org/papers/IJSDR2104117.pdf |
| Downloads: | 000337071 |
| Publication Details: | Published Paper ID: IJSDR2104117 Registration ID:193255 Published In: Volume 6 Issue 4, April-2021 DOI (Digital Object Identifier): Page No: 700 - 704 Publisher: IJSDR | www.ijsdr.org ISSN Number: 2455-2631 |
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