International Journal of Scientific Development and Research - IJSDR
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Authors Name: CH.TANUJA , J. Lakshmi Aparna
Unique Id: IJSDR2008005
Published In: Volume 5 Issue 8, August-2020
Abstract: Now a days, in the field of Very Large Scale Integration (VLSI), Power and Speed became more constrained parameters. In order to achieve better performance, one has to prefer low power and high speed designs only. There are different types of adiabatic logic circuit used for low power consumption. The comparative power consumption of adiabatic logic using Two Phase Adiabatic Static Clocked logic (2PASCL) and Positive Feedback Adiabatic Logic (PFAL) is proposed here. In digital design flip flops are the main components responsible for storing in all SOCs. The power consumption of D-Flip flop and Shift Register is compared using both the adiabatic topologies. Which is extracted from previous adiabatic logic circuits such as ECRL and 2N2N2P. The proposed design exhibits less power and high speed over existing designs. A lot of research has been done on the adiabatic logic based designs and our design leads better results. The designs are simulated in 180nm CMOS Technology and Schematic designed using Tanner EDA
Keywords: CMOS, PFAL, 2PASCL, ECRL. 2N2N2P, Tanner EDA, VLSI
Cite Article: "DESIGN and IMPLEMENTATION of 8 Bit-SHIFT REGISTER by Using TWO PHASE ADIABATIC STATIC CLOCKED LOGIC ", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.5, Issue 8, page no.32 - 37, August-2020, Available :http://www.ijsdr.org/papers/IJSDR2008005.pdf
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Publication Details: Published Paper ID: IJSDR2008005
Registration ID:192217
Published In: Volume 5 Issue 8, August-2020
DOI (Digital Object Identifier):
Page No: 32 - 37
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631

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