Floating Point Addition, Subtraction and Multiplication on FPGA
G. Mohana Durga
, D. Bhavani
Field Programmable Gate Array, Hardware Implementation, Float Point Arithmetic, Xilinx, Verilog HDL.
Floating point operations are widely used in many applications and in different areas to perform mathematical operations very accurately, Digital Signal Processing and Digital Image Processing algorithms. These operations are hard to implement on Field Programmable Gate Arrays (FPGAs) because of the complexity of their algorithms but many scientific problems require floating point arithmetic with high levels of accuracy in their calculations. Floating point arithmetic architecture is designed and implemented on FPGA become easier by using high level language such as Verilog HDL. This paper explores FPGA implementations of addition, subtraction and multiplication for IEEE-754 single precision floating point numbers. Here 24 bit multiplier is designed with small 4 bit multipliers. The implementation is performed using Xilinx’s Spartan 3 FPGAs.
"Floating Point Addition, Subtraction and Multiplication on FPGA", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.3, Issue 7, page no.20 - 24, July-2018, Available :https://ijsdr.org/papers/IJSDR1807003.pdf
Volume 3
Issue 7,
July-2018
Pages : 20 - 24
Paper Reg. ID: IJSDR_180469
Published Paper Id: IJSDR1807003
Downloads: 000346998
Research Area: Engineering
Country: -, -, -
ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publisher: IJSDR(IJ Publication) Janvi Wave
