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INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH
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ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
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Paper Title:	Floating Point Addition, Subtraction and Multiplication on FPGA
Authors Name:	G. Mohana Durga , D. Bhavani
Unique Id:	IJSDR1807003
Published In:	Volume 3 Issue 7, July-2018
Abstract:	Floating point operations are widely used in many applications and in different areas to perform mathematical operations very accurately, Digital Signal Processing and Digital Image Processing algorithms. These operations are hard to implement on Field Programmable Gate Arrays (FPGAs) because of the complexity of their algorithms but many scientific problems require floating point arithmetic with high levels of accuracy in their calculations. Floating point arithmetic architecture is designed and implemented on FPGA become easier by using high level language such as Verilog HDL. This paper explores FPGA implementations of addition, subtraction and multiplication for IEEE-754 single precision floating point numbers. Here 24 bit multiplier is designed with small 4 bit multipliers. The implementation is performed using Xilinx’s Spartan 3 FPGAs.
Keywords:	Field Programmable Gate Array, Hardware Implementation, Float Point Arithmetic, Xilinx, Verilog HDL.
Cite Article:	"Floating Point Addition, Subtraction and Multiplication on FPGA", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.3, Issue 7, page no.20 - 24, July-2018, Available :http://www.ijsdr.org/papers/IJSDR1807003.pdf
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Publication Details:	Published Paper ID: IJSDR1807003 Registration ID:180469 Published In: Volume 3 Issue 7, July-2018 DOI (Digital Object Identifier): Page No: 20 - 24 Publisher: IJSDR \| www.ijsdr.org ISSN Number: 2455-2631

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