BIST Memory Design and Testing

S.Divya , S.Tamil selvan , A.Selva kumar , V.Suresh kumar

Memory, BIST,LFSR,Test data

Memories are the most essential component in all storage devices. Memory structure become complex when it is upgrading. Due to higher level of integration in memory size, manufacturing cost of the device is reducing and testing cost is increasing. Testing is needed to give the fault free products. Large number of bit pattern requires more time to test the circuit. Test algorithms are necessary to minimize the testing time. In this paper memory is designed and tested for stuck at fault with single bit and multiple bit error. We have simulated and analyzed the memory design using Xilinx design suite ISE 14.2.

Published Paper   E-Certificate

"BIST Memory Design and Testing", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.3, Issue 4, page no.101 - 106, April-2018, Available :https://ijsdr.org/papers/IJSDR1804018.pdf

Volume 3 Issue 4, April-2018

Pages : 101 - 106

Paper Reg. ID: IJSDR_180130

Published Paper Id: IJSDR1804018

Downloads: 000347091

Research Area: Engineering

Country: Coimbatore, Tamil nadu, India

Published Paper PDF: https://ijsdr.org/papers/IJSDR1804018

Published Paper URL: https://ijsdr.org/viewpaperforall?paper=IJSDR1804018

ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Publisher: IJSDR(IJ Publication) Janvi Wave

This work is licensed under a Creative Commons Attribution 4.0 International License and The Open Definition