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INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH
International Peer Reviewed & Refereed Journals, Open Access Journal
ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15

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Paper Title:	BIST Memory Design and Testing
Authors Name:	S.Divya , S.Tamil selvan , A.Selva kumar , V.Suresh kumar
Unique Id:	IJSDR1804018
Published In:	Volume 3 Issue 4, April-2018
Abstract:	Memories are the most essential component in all storage devices. Memory structure become complex when it is upgrading. Due to higher level of integration in memory size, manufacturing cost of the device is reducing and testing cost is increasing. Testing is needed to give the fault free products. Large number of bit pattern requires more time to test the circuit. Test algorithms are necessary to minimize the testing time. In this paper memory is designed and tested for stuck at fault with single bit and multiple bit error. We have simulated and analyzed the memory design using Xilinx design suite ISE 14.2.
Keywords:	Memory, BIST,LFSR,Test data
Cite Article:	"BIST Memory Design and Testing", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.3, Issue 4, page no.101 - 106, April-2018, Available :http://www.ijsdr.org/papers/IJSDR1804018.pdf
Downloads:	000346980
Publication Details:	Published Paper ID: IJSDR1804018 Registration ID:180130 Published In: Volume 3 Issue 4, April-2018 DOI (Digital Object Identifier): Page No: 101 - 106 Publisher: IJSDR \| www.ijsdr.org ISSN Number: 2455-2631

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