INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15
Design and Implementation of an Area Efficient Interleaver for MIMO-OFDM Systems
Authors Name:
D.Nagaraju
Unique Id:
IJSDR1708008
Published In:
Volume 2 Issue 8, August-2017
Abstract:
This work is based on a memory-efficient and faster interleaver implementation technique for MIMO- OFDM communication systems on FPGA. The IEEE 802.16 standard is used as a reference for simulation and analysis . This is the method for interleaver design on FPGA and its memory utilization. This project work concentrate on efficient interleaver design for IEEE 802.16 system implemented on FPGA. Our goal is to achieve minimum memory us age, faster interleaving, and increased s peed of the overall system.
Keywords:
MIMO-OFDM, IEEE 802.16, FEC, INTERLEAVING
Cite Article:
"Design and Implementation of an Area Efficient Interleaver for MIMO-OFDM Systems", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.2, Issue 8, page no.44 - 48, August-2017, Available :http://www.ijsdr.org/papers/IJSDR1708008.pdf
Downloads:
000337073
Publication Details:
Published Paper ID: IJSDR1708008
Registration ID:170649
Published In: Volume 2 Issue 8, August-2017
DOI (Digital Object Identifier):
Page No: 44 - 48
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631
Facebook Twitter Instagram LinkedIn