Design of an enhanced fault tolerant ALU using hardware redundancy technique for low power applications
Mary Swarna Latha Gade
, K Sreenivasa Ravi
fault tolerant ALU, Tripler Modular Redundancy, Clock gating, VHDL
The recent advances in the semiconductor industry have led in the development of more complex components and systems’ architectures by allowing fabrication processes to place a higher number of transistors per area of the silicon die .Thus the manufacturing process are less and less reliable. Therefore we need to build systems that will acknowledge the existence of faults and incorporate techniques to tolerate these faults while still delivering an acceptable level of service. In this paper, we design fault tolerant 16-bit Arithmetic and Logical Unit (ALU) circuit using a hard ware redundancy technique namely TMR (Triple Modular Redundancy) technique in which three modules are replicated and given to voter logic. Also we design ALU to achieve less power consumption and highly reliable using Clock Gating. The software used is XilinxISE
"Design of an enhanced fault tolerant ALU using hardware redundancy technique for low power applications ", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.2, Issue 5, page no.422 - 425, May-2017, Available :https://ijsdr.org/papers/IJSDR1705076.pdf
Volume 2
Issue 5,
May-2017
Pages : 422 - 425
Paper Reg. ID: IJSDR_170451
Published Paper Id: IJSDR1705076
Downloads: 000347028
Research Area: Engineering
Country: Hyderarbad, Telangana, India
ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publisher: IJSDR(IJ Publication) Janvi Wave