INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15
Design of an enhanced fault tolerant ALU using hardware redundancy technique for low power applications
Authors Name:
Mary Swarna Latha Gade
, K Sreenivasa Ravi
Unique Id:
IJSDR1705076
Published In:
Volume 2 Issue 5, May-2017
Abstract:
The recent advances in the semiconductor industry have led in the development of more complex components and systems’ architectures by allowing fabrication processes to place a higher number of transistors per area of the silicon die .Thus the manufacturing process are less and less reliable. Therefore we need to build systems that will acknowledge the existence of faults and incorporate techniques to tolerate these faults while still delivering an acceptable level of service. In this paper, we design fault tolerant 16-bit Arithmetic and Logical Unit (ALU) circuit using a hard ware redundancy technique namely TMR (Triple Modular Redundancy) technique in which three modules are replicated and given to voter logic. Also we design ALU to achieve less power consumption and highly reliable using Clock Gating. The software used is XilinxISE
"Design of an enhanced fault tolerant ALU using hardware redundancy technique for low power applications ", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.2, Issue 5, page no.422 - 425, May-2017, Available :http://www.ijsdr.org/papers/IJSDR1705076.pdf
Downloads:
000346987
Publication Details:
Published Paper ID: IJSDR1705076
Registration ID:170451
Published In: Volume 2 Issue 5, May-2017
DOI (Digital Object Identifier):
Page No: 422 - 425
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631
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