INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15
Efficient Design of Shift Register for Area and Power Reduction Using Pulsed Latch
Authors Name:
KALAIVANI S
, Dr. R. SATYABAMA
Unique Id:
IJSDR1703015
Published In:
Volume 2 Issue 3, March-2017
Abstract:
A shift register is a basic building block in VLSI circuits. Shift registers are commonly used in many applications, such as digital filters, communication receivers and image processing. The architecture of a shift registers is quite simple. An N-bit shift register is composed of a series connected N data flip-flops. The speed of the flip-flop is less important than the area and power consumption. Because there is no circuit between flip-flop in the shift register. The smallest flip-flop is suitable for the shift register to reduce the area and power consumption. Recently, pulsed latches are replaced flip-flops in many applications, because a pulsed latch is much smaller than a flip-flop and it cannot be used in a shift register due to the timing problem between pulsed latches. To overcome this problem, multiple non overlap delayed pulsed clock signals are used instead of the conventional single pulsed clock signal. The shift registers use a small number of the pulsed clock signals by grouping the latches to
"Efficient Design of Shift Register for Area and Power Reduction Using Pulsed Latch", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.2, Issue 3, page no.88 - 97, March-2017, Available :http://www.ijsdr.org/papers/IJSDR1703015.pdf
Downloads:
000336256
Publication Details:
Published Paper ID: IJSDR1703015
Registration ID:170078
Published In: Volume 2 Issue 3, March-2017
DOI (Digital Object Identifier):
Page No: 88 - 97
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631
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