PERFORMANCE ANALYSIS OF DIFFERENT ADIABATIC LOGIC FAMILIES
ANITHA K
, Dr. MEENA SRINIVASAN
Adiabatic logic; CMOS Logic; MUX;Tanner EDA tool;Power dissipation
With the increase in demand of portable electronic devices, it is necessary to design circuits with low power dissipation. Adiabatic logic design satisfies this need of low power dissipation by reducing power due to unwanted switching activity. Adiabatic logic state refers to the change of state that occurs without gain or loss of heat. Some of the partial and fully adiabatic logic families are analyzed with 2*1 multiplexer using Tanner EDA tool. All the adiabatic logic families achieve reduction in power dissipation compared with conventional CMOS logic. Among the adiabatic logic circuits, Positive Feedback Adiabatic Logic (PFAL) design results in 80% of power reduction when compared with conventional CMOS logic. Hence, 4*1 and 8*1 multiplexers are designed with PFAL logic which results in 42% and 39% of power reduction respectively.
"PERFORMANCE ANALYSIS OF DIFFERENT ADIABATIC LOGIC FAMILIES", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.2, Issue 3, page no.73 - 80, March-2017, Available :https://ijsdr.org/papers/IJSDR1703013.pdf
Volume 2
Issue 3,
March-2017
Pages : 73 - 80
Paper Reg. ID: IJSDR_170079
Published Paper Id: IJSDR1703013
Downloads: 000347242
Research Area: Engineering
Country: ERODE, Tamil Nadu, India
ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publisher: IJSDR(IJ Publication) Janvi Wave
