Paper Title

Modified Low Power and High Speed Row and Column Bypass Multiplier using FPGA

Authors

Amala Maria Alex , Nidhish Antony

Keywords

FFT-Fast Fourier Transform,DSP-Discrete Cosine Transform,DSP-Digital signal processing,CSM-Carry Save Multiplier, CSA-Carry Select Adder, ADPCM-Adaptive Differential Pulse Code Modulation, QC-Quantum Cost, GO-Garbage Output, NC-Number of constant input.

Abstract

The demand for electronic portable devices is gaining more attention in recent decades. Portable devices are demanding for low power. Multiplier is the critical part of any arithmetic operation in many DSP applications. So it is essential to design multipliers that utilize less power and high speed of operation. One main aspect of low power design is to minimize switching activities to reduce dynamic power dissipation. So the proposed bypassing logic will reduce dynamic power dissipation as well as signal propagation delay. Row and column bypass multiplier is a new design which reduces switching activities with architecture optimization. The switching activity should not occur unnecessarily and it should be avoided by bypassing. The adders corresponding to those rows and columns which are required to be bypassed need not get activated and signal get bypassed to the further stage. With the help of tristate buffer as a control gating element, unnecessary signal propagation can be stopped. Thus the unwanted switching activity can be reduced. The proposed multiplier design is efficient in terms of power by 20% or more when probability of occurrence of zero is more. These features make the proposed design more suitable for DSP applications like filtering, DCT and FFT.

How To Cite

"Modified Low Power and High Speed Row and Column Bypass Multiplier using FPGA", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.1, Issue 7, page no.256 - 263, July-2016, Available :https://ijsdr.org/papers/IJSDR1607044.pdf

Issue

Volume 1 Issue 7, July-2016

Pages : 256 - 263

Other Publication Details

Paper Reg. ID: IJSDR_160626

Published Paper Id: IJSDR1607044

Downloads: 000346998

Research Area: Engineering

Country: KOTTAYAM, Kerala, India

Published Paper PDF: https://ijsdr.org/papers/IJSDR1607044

Published Paper URL: https://ijsdr.org/viewpaperforall?paper=IJSDR1607044

About Publisher

ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Publisher: IJSDR(IJ Publication) Janvi Wave

Article Preview

academia
publon
sematicscholar
googlescholar
scholar9
maceadmic
Microsoft_Academic_Search_Logo
elsevier
researchgate
ssrn
mendeley
Zenodo
orcid
sitecreex