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ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
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Paper Title: Customized Controller Design of Partitioned DDR SDRAM for RF Data Acquisition System
Authors Name: Bhargav B Kulkarni , Veena N , Girish G K
Unique Id: IJSDR1607041
Published In: Volume 1 Issue 7, July-2016
Abstract: DDR SDRAM (Double Data Rate Synchronous Dynamic RAM) controllers are used to control and command the operations such as recording and reading of data from DDR SDRAM. In real time data acquisition system, the data needs to be stored at very high speed and in environments of outer space. High speed ADCs (Analog to Digital Convertors) are used to convert incoming analog data into digital data for further processing to estimate various pulse parameters. Due to effects like Single Event Upsets (SEU), re-programmable FPGAs cannot be used but high speed OTPs (One Time Programmable) such as Actel FPGA (Field Programmable Gate Arrays) is used for designing the controller.
Keywords: DDR SDRAM, Data Acquisition, SEU, OTP Actel FPGA
Cite Article: "Customized Controller Design of Partitioned DDR SDRAM for RF Data Acquisition System ", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.1, Issue 7, page no.233 - 237, July-2016, Available :http://www.ijsdr.org/papers/IJSDR1607041.pdf
Downloads: 000101746
Publication Details: Published Paper ID: IJSDR1607041
Registration ID:160632
Published In: Volume 1 Issue 7, July-2016
DOI (Digital Object Identifier):
Page No: 233 - 237
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631

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