Survey of Scan Chain based Low Power Testing

Rashmi K.M , Dr.K.N.Muralidhara

BIST, Design for testability, scan chain masking, scan based testing

In the area of VLSI testing chip failure can occur anywhere, it can be in the flip flops, combinational circuitry or even the Design for testability (DFT) circuitry such as scan chain and logic BIST. Scan chains can be touted as effective aid for logic circuit testing and diagnosis and maximum chip failures occurs due to the defects in the scan chains. This survey is mainly focused on the scan chain defects and scan chain masking for diagnosis of failures in scan based testing.

Published Paper   E-Certificate

"Survey of Scan Chain based Low Power Testing", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.1, Issue 7, page no.125 - 127, July-2016, Available :https://ijsdr.org/papers/IJSDR1607020.pdf

Volume 1 Issue 7, July-2016

Pages : 125 - 127

Paper Reg. ID: IJSDR_160605

Published Paper Id: IJSDR1607020

Downloads: 000346998

Research Area: Engineering

Country: Belthangady, D.K, Karnataka, India

Published Paper PDF: https://ijsdr.org/papers/IJSDR1607020

Published Paper URL: https://ijsdr.org/viewpaperforall?paper=IJSDR1607020

ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Publisher: IJSDR(IJ Publication) Janvi Wave

This work is licensed under a Creative Commons Attribution 4.0 International License and The Open Definition