Implementation of FFT Algorithm Based on Vedic Maths Using FPGA
Vishal Rajeshkumar Panchal
, Prof. Milind Shah
FFT, Vedic Mathematics, Vedic Multiplier, UrthvaTiryagbhyam, Vertically and Crosswise Algorithm.
Abstract—This Fast Fourier transform (FFT) is an efficient algorithm to compute the N point DFT. The FFT is a computationally intensive digital signal processing function, but the Implementation of FFT requires large number of complex multiplications, so to make this process rapid and simple, it is necessary for a multiplier to be fast and power efficient. To solve this problem, UrdhvaTiryagbhyam sutra in Vedic mathematics is used. It is based on a concept through which the generation of all partial products can be done and then, concurrent addition of these partial products can be done. The conventional multiplication method requires more time & area than Vedic algorithms. In this paper, the algorithm for FFT using Vedic maths is proposed.
"Implementation of FFT Algorithm Based on Vedic Maths Using FPGA", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.1, Issue 5, page no.265 - 269, May-2016, Available :https://ijsdr.org/papers/IJSDR1605052.pdf
Volume 1
Issue 5,
May-2016
Pages : 265 - 269
Paper Reg. ID: IJSDR_160329
Published Paper Id: IJSDR1605052
Downloads: 000347057
Research Area: Engineering
Country: Ahmedabad, Gujarat, India
ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publisher: IJSDR(IJ Publication) Janvi Wave
