A 10 Bit, Low Power ADC Suitable for Wireless Application
Mr. Prabhao Fulzele
, Mr. Bhagwat Kakde
Successive Approximation Register (SAR),Low power, Resolution, Sampling Rate.
This Paper presents the Design of analog to digital converter (ADC) for wireless applications, so here is the selection of right architecture is very crucial. We have chosen successive approximation Analog to Digital Converter because of their compact circuitry as compared with the Flash ADC which makes this SAR ADC inexpensive. Day By Day more and more applications are built on the basis of power consumption so this SAR ADC will be useful for high speed with medium resolution and low power consumption. The Successive Approximation (SAR) architecture is very suitable for data acquisition, it has resolutions ranging from 8 bits to 12 bits and sampling rates ranging from 50 KHz to 50 MHz.
"A 10 Bit, Low Power ADC Suitable for Wireless Application", IJSDR - International Journal of Scientific Development and Research (www.IJSDR.org), ISSN:2455-2631, Vol.1, Issue 5, page no.13 - 17, May-2016, Available :https://ijsdr.org/papers/IJSDR1605003.pdf
Volume 1
Issue 5,
May-2016
Pages : 13 - 17
Paper Reg. ID: IJSDR_160120
Published Paper Id: IJSDR1605003
Downloads: 000347068
Research Area: Engineering
Country: nagpur, maharastra, India
ISSN: 2455-2631 | IMPACT FACTOR: 9.15 Calculated By Google Scholar | ESTD YEAR: 2016
An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 9.15 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator
Publisher: IJSDR(IJ Publication) Janvi Wave
