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ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
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Issue: January 2023

Volume 8 | Issue 1

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Paper Title: Implementation of ALU using 10T Full Adder using Cell based Technology
Authors Name: A Sowjanya
Unique Id: IJSDR1604067
Published In: Volume 1 Issue 4, April-2016
Abstract: As technology diminishes into the nanometer scales leakage current, active power, delay and area are plays an important role in the analysis and design of complex circuits. For battery based systems like mobiles, laptops etc., current and power dissipations are major factors. A transistor resizing approach with sleep transistor technology for 10 transistor single bit full adder cells is used to reduce power dissipation and leakage current. In this paper ALU is designed by using a submicron level 10-transistor single bit full adder cell is used to achieve low leakage current, reduced power dissipation and high speed on cadence 180nm technology.
Keywords: leakage current, 10T full adder, sleep transistors, ALU, submicron.
Cite Article: "Implementation of ALU using 10T Full Adder using Cell based Technology", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.1, Issue 4, page no.378 - 381, April-2016, Available :http://www.ijsdr.org/papers/IJSDR1604067.pdf
Downloads: 000201509
Publication Details: Published Paper ID: IJSDR1604067
Registration ID:160226
Published In: Volume 1 Issue 4, April-2016
DOI (Digital Object Identifier):
Page No: 378 - 381
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631

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