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INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH
International Peer Reviewed & Refereed Journals, Open Access Journal
ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
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Paper Title:	Design of a Parallel Self-Timed Adder using Recursive approach
Authors Name:	M.Pravallika , V.Suresh
Unique Id:	IJSDR2007034
Published In:	Volume 5 Issue 7, July-2020
Abstract:	Adders finds applications in circuits like microprocessors, memory units, ALU’s etc. In this project, the design and performance of Parallel Self-Timed Adder is presented. In the proposed work mainly aimed at minimizing the number of transistors and estimation of various parameters viz., area, power, delay for PASTA. We have also designed 2 bit PASTA as an example of proposed approach. Simulations are carried out using HSPICE. The resuls agree with the theoretical one
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Cite Article:	"Design of a Parallel Self-Timed Adder using Recursive approach", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.5, Issue 7, page no.261 - 268, July-2020, Available :http://www.ijsdr.org/papers/IJSDR2007034.pdf
Downloads:	000337064
Publication Details:	Published Paper ID: IJSDR2007034 Registration ID:192025 Published In: Volume 5 Issue 7, July-2020 DOI (Digital Object Identifier): Page No: 261 - 268 Publisher: IJSDR \| www.ijsdr.org ISSN Number: 2455-2631

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