INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15
PERFORMANCE ANALYSIS OF DIFFERENT ADIABATIC LOGIC FAMILIES
Authors Name:
ANITHA K
, Dr. MEENA SRINIVASAN
Unique Id:
IJSDR1703013
Published In:
Volume 2 Issue 3, March-2017
Abstract:
With the increase in demand of portable electronic devices, it is necessary to design circuits with low power dissipation. Adiabatic logic design satisfies this need of low power dissipation by reducing power due to unwanted switching activity. Adiabatic logic state refers to the change of state that occurs without gain or loss of heat. Some of the partial and fully adiabatic logic families are analyzed with 2*1 multiplexer using Tanner EDA tool. All the adiabatic logic families achieve reduction in power dissipation compared with conventional CMOS logic. Among the adiabatic logic circuits, Positive Feedback Adiabatic Logic (PFAL) design results in 80% of power reduction when compared with conventional CMOS logic. Hence, 4*1 and 8*1 multiplexers are designed with PFAL logic which results in 42% and 39% of power reduction respectively.
"PERFORMANCE ANALYSIS OF DIFFERENT ADIABATIC LOGIC FAMILIES", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.2, Issue 3, page no.73 - 80, March-2017, Available :http://www.ijsdr.org/papers/IJSDR1703013.pdf
Downloads:
000337070
Publication Details:
Published Paper ID: IJSDR1703013
Registration ID:170079
Published In: Volume 2 Issue 3, March-2017
DOI (Digital Object Identifier):
Page No: 73 - 80
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631
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