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INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016 open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15 |
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| Paper Title: | An Efficient VLSI Architecture of a Clock-gating Turbo Decoder for Wireless Sensor Network Applications |
| Authors Name: | G DIVYA BHARATHI , SURENDRA.S |
| Unique Id: | IJSDR1610027 |
| Published In: | Volume 1 Issue 10, October-2016 |
| Abstract: | Wireless sensor network can be considered to be energy constrained wireless scenarios, since the sensors are operated for extended periods of time, while relying on batteries that are small, lightweight and inexpensive. The conventional turbo decoder architecture requires high chip area and hence high power consumption. This motivated the proposed system to design the decoder architecture with high throughput, less decoding iteration and less memory requirement. Clock gating is a technique that can be used to control the power dissipated by clock net. The proposed work is implemented using clock gating technique in order to reduce the power consumption. The previous turbo decoder architectures uses optimal-log based algorithm which has the complexity about 75% and hence leads to time and energy consumption due to sequential operations. Whereas the proposed architecture uses the fundamental Add Compare Select (ACS) operation. Due to the parallel processing operation of ACS blocks the proposed architecture tend to have low processing steps, so that low transmission energy and less complexity about 71%. The proposed work implementation has a throughput of 1.03 Mb/s, memory requirement of 128 Kbps, power consumption of about 0.016(mV) and requires 0.010(A) of current. Comparing to the optimal-log based algorithm in the proposed lookup table based architecture the complexity is reduced by 4% and by implementing the clock-gating technique the power consumption is reduced by 38%.1G DIVYA BHARATHI |
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| Cite Article: | "An Efficient VLSI Architecture of a Clock-gating Turbo Decoder for Wireless Sensor Network Applications", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.1, Issue 10, page no.149 - 165, October-2016, Available :http://www.ijsdr.org/papers/IJSDR1610027.pdf |
| Downloads: | 000337213 |
| Publication Details: | Published Paper ID: IJSDR1610027 Registration ID:160890 Published In: Volume 1 Issue 10, October-2016 DOI (Digital Object Identifier): Page No: 149 - 165 Publisher: IJSDR | www.ijsdr.org ISSN Number: 2455-2631 |
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