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Paper Title: Modified Low Power and High Speed Row and Column Bypass Multiplier using FPGA
Authors Name: Amala Maria Alex , Nidhish Antony
Unique Id: IJSDR1607044
Published In: Volume 1 Issue 7, July-2016
Abstract: The demand for electronic portable devices is gaining more attention in recent decades. Portable devices are demanding for low power. Multiplier is the critical part of any arithmetic operation in many DSP applications. So it is essential to design multipliers that utilize less power and high speed of operation. One main aspect of low power design is to minimize switching activities to reduce dynamic power dissipation. So the proposed bypassing logic will reduce dynamic power dissipation as well as signal propagation delay. Row and column bypass multiplier is a new design which reduces switching activities with architecture optimization. The switching activity should not occur unnecessarily and it should be avoided by bypassing. The adders corresponding to those rows and columns which are required to be bypassed need not get activated and signal get bypassed to the further stage. With the help of tristate buffer as a control gating element, unnecessary signal propagation can be stopped. Thus the unwanted switching activity can be reduced. The proposed multiplier design is efficient in terms of power by 20% or more when probability of occurrence of zero is more. These features make the proposed design more suitable for DSP applications like filtering, DCT and FFT.
Keywords: FFT-Fast Fourier Transform,DSP-Discrete Cosine Transform,DSP-Digital signal processing,CSM-Carry Save Multiplier, CSA-Carry Select Adder, ADPCM-Adaptive Differential Pulse Code Modulation, QC-Quantum Cost, GO-Garbage Output, NC-Number of constant input.
Cite Article: "Modified Low Power and High Speed Row and Column Bypass Multiplier using FPGA", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.1, Issue 7, page no.256 - 263, July-2016, Available :http://www.ijsdr.org/papers/IJSDR1607044.pdf
Downloads: 0001420
Publication Details: Published Paper ID: IJSDR1607044
Registration ID:160626
Published In: Volume 1 Issue 7, July-2016
DOI (Digital Object Identifier):
Page No: 256 - 263
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631

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