INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016
open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15
A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor
Authors Name:
M. Raj Lahari
, K. Neeharika
Unique Id:
IJSDR1606029
Published In:
Volume 1 Issue 6, June-2016
Abstract:
This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the number of data bits.The circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant inputs, garbage outputs and quantum cost of the reversible fault tolerant decoder have been proposed. Transistor simulations of the proposed decoder are shown using standard p-MOS 901 and n-MOS 902 model with delay of 0.030 ns and 0.12 μm channel length, which proved the functional correctness of the proposed circuits. The comparative results show that the proposed design is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability than the existing approach.
"A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.1, Issue 6, page no.142 - 147, June-2016, Available :http://www.ijsdr.org/papers/IJSDR1606029.pdf
Downloads:
000336255
Publication Details:
Published Paper ID: IJSDR1606029
Registration ID:160509
Published In: Volume 1 Issue 6, June-2016
DOI (Digital Object Identifier):
Page No: 142 - 147
Publisher: IJSDR | www.ijsdr.org
ISSN Number: 2455-2631
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