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INTERNATIONAL JOURNAL OF SCIENTIFIC DEVELOPMENT AND RESEARCH International Peer Reviewed & Refereed Journals, Open Access Journal ISSN Approved Journal No: 2455-2631 | Impact factor: 8.15 | ESTD Year: 2016 open access , Peer-reviewed, and Refereed Journals, Impact factor 8.15 |
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| Paper Title: | A Low Power 4X 4 Multiplier Design using (5-T)Half Adder,(8-T)Full Adder &(2-T) AND Gate |
| Authors Name: | Prof. M.Raj Lahari , Prof. K.Neeharika |
| Unique Id: | IJSDR1605097 |
| Published In: | Volume 1 Issue 5, May-2016 |
| Abstract: | In this paper, we propose a new technique for implementing a low power high speed multiplier using full adder consisting of minimum no. of transistors (8-T). Multiplier circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the multiplier. Simulated results indicate the superior performance of the proposed technique over conventional CMOS multiplier. Detailed comparison of simulated results for the conventional and present method of implementation is presented. |
| Keywords: | 2-T AND; 8-T Full Adder; 4x4 Multiplier; 2-T MUX; Pass transistor logic; 3-T XOR; |
| Cite Article: | "A Low Power 4X 4 Multiplier Design using (5-T)Half Adder,(8-T)Full Adder &(2-T) AND Gate", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.1, Issue 5, page no.506 - 510, May-2016, Available :http://www.ijsdr.org/papers/IJSDR1605097.pdf |
| Downloads: | 000337212 |
| Publication Details: | Published Paper ID: IJSDR1605097 Registration ID:160372 Published In: Volume 1 Issue 5, May-2016 DOI (Digital Object Identifier): Page No: 506 - 510 Publisher: IJSDR | www.ijsdr.org ISSN Number: 2455-2631 |
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